Verilog

UART Transceiver in Verilog

A UART transmitter and receiver (8N1) written from scratch in Verilog, built from counters, shift registers and state machines, and verified with a self-checking loopback testbench in Icarus Verilog.

• Full 8N1 serial link in Verilog: a parameterised baud generator, a transmitter and a receiver
• Receiver uses 16x oversampling and a two-flop synchroniser to sample every bit at its centre
• Self-checking loopback testbench: 13 bytes, including a back-to-back burst, all received with zero errors
• Found and fixed a start-bit timing bug that shifted every sample half a bit early