Simulation
UART Transceiver in Verilog
A UART transmitter and receiver (8N1) written from scratch in Verilog, built from counters, shift registers and state machines, and verified with a self-checking loopback testbench in Icarus Verilog.
- Full 8N1 serial link in Verilog: a parameterised baud generator, a transmitter and a receiver
- Receiver uses 16x oversampling and a two-flop synchroniser to sample every bit at its centre
- Self-checking loopback testbench: 13 bytes, including a back-to-back burst, all received with zero errors
- Found and fixed a start-bit timing bug that shifted every sample half a bit early
Operational Amplifier in LTSpice
Spent a few months teaching myself the internal layout of an OpAmp, then built one from scratch out of individual transistors in LTSpice.
- Learned and built every stage myself: differential pair, current mirrors, and a push-pull power stage
- Tested it by stepping the feedback resistor through four values and checking the gain against theory
- Measured gain matched the predicted Rf/Rin ratio almost exactly, even at ×1000